ASPADIP Logo

Supervisor: Germain PHAM dpham at telecom-paris.fr

Project topics : Signal processing, Electrical engineering, Computer Engineering

Number of students: 2

Project description

Dive into the exciting world of signal processing and embedded system design with this hands-on project! Using state-of-the-art Analog Devices SDR platforms, including the Pluto SDR and Zynq/ZynqMP systems, you will develop and validate signal processing workflows and gain expertise in cutting-edge hardware and software tools.

Participants will work on transmitting and receiving ADI signals, performing error analysis, building HDL projects for transceiver modules, and validating operations using the IIO Oscilloscope tool and the pyadi Python package. The project also emphasizes effective bug reporting and collaborative problem-solving using GitHub and other collaborative structures.

Key Features:

  • ADALM-Pluto SDR platform:

  • Generate and transmit ADI signals via Pluto SDR and receive them for error analysis.

  • Identify non-flat errors in transmitted and received signals.

  • Develop clear and actionable bug reports for GitHub and Engineering Zone.

  • "Zynq FPGA + AD936x" and "ZynqMP FPGA + AD9988" SDR Platforms:

  • Build and implement the HDL project to control the SDR chips transceiver using each target FPGA.

  • Use the IIO Oscilloscope to validate the system’s functionality and performance.

  • Use the pyadi Python package to automate the system’s operation and data collection.

Required skills

This project requires a good knowledge of signal processing, electrical engineering, computer engineering.

  • Mandatory

    • Python programming experience (setting a virtual environment or LD_LIBRARY_PATH or PYTHONPATH)

    • practical elements of git

    • Understanding the standard build process of softwares or HDL project (using make (GNU make))

    • Linux OS basics (usage of terminal command lines)

      • Using ssh to connect to a remote server

    • Strong background of signal processing and digital communications

  • Optional

    • basic knowledge of transceivers and SDR platforms

    • Familiarity with FPGA toolchains like Vivado or Quartus

Please note that no VHDL or Verilog programming is required for this project. Only the build process must be understood.

Workplan (5 weeks)

gantt
title ICS Project: ASPADIP
dateFormat DD/MM/YYYY
excludes weekends
axisFormat %e %b %y
tickInterval 1week
weekday monday
todayMarker off
 
section Week1 - Initial Setup and Familiarization
Set up the development environment - pyadi, IIO Oscilloscope, latex, sshfs: 25/02/2025, 1d
Gain familiarity with the AD936x and AD9988 transceivers: 26/02/2025, 2d
Test Pluto SDR with basic TX-RX signals to verify setup - IIO Osc, pyadi: 28/02/2025, 2d
Deliverable slides - Synthesis of the basic TX/RX signals: milestone, 03/03/2025, 1d
section Week2 - Pluto SDR Signal Transmission and Analysis
Develop a script to transmit and receive signals using Pluto SDR: 03/03/2025, 1d
Analyze error characteristics and document non-flat errors: 04/03/2025, 2d
Write preliminary bug reports on GitHub and Engineering Zone: 06/03/2025, 2d
Deliverable slides - Github issue: milestone, 07/03/2025, 1d
section Week3+4 - Zynq + ZynqMP FPGA HDL Dev and Test
[Zynq] Build and test the HDL project to interface the Zynq FPGA with AD936x: 10/03/2025, 1d
[Zynq] Test system operation using IIO Oscilloscope and pyadi: 11/03/2025, 4d
[ZynqMP] Build and test the HDL project to interface the ZynqMP FPGA with AD9988: 17/03/2025, 1d
[ZynqMP] Test system operation using IIO Oscilloscope and pyadi: 18/03/2025, 4d
Deliverable slides - Test results for each platform: milestone, 21/03/2025, 1d
section Week5 - Open source contribution
Code refactoring and documentation: 24/03/2025, 2d
Gitlab release: milestone, 27/03/2025, 1d
Slides preparation: 24/03/2025, 2d
Project defense: milestone, 28/03/2025, 1d

Location

School

Télécom Paris trains its students to innovate in today’s digital world. Its training and research cover all fields of information and communication sciences and technologies with a strong societal foundation in order to address the major challenges of the 21st century. Its offers engineering, PhD and professional degree programs, with international students accounting for 55% of its student body. Its research offers original, multidisciplinary world-class expertise in nine strategic areas: Data Science and Artificial Intelligence — Visual and Audio Computing, Interaction — Digital Trust — Innovation Regulations — Transformation of Innovative Firms — Cyber-Physical Systems — Communication Systems and Networks — Mathematics and Applications — Uses, Participation, Democratization of Innovation.

As a founding member of Institut Polytechnique de Paris and an IMT (Institut Mines-Télécom) school, Télécom Paris is a living laboratory that fosters practical solutions and applications while measuring their impact on society.

location_on Address: 19 place Marguerite Perey, 91120 Palaiseau, France

Find us on Google Maps

Hosting laboratory

Laboratoire Traitement et Communication de l’Information (LTCI)

Research team

The Circuits et Systèmes de Communication (C2S) team is internationally recognized for its ability to integrate digital intelligence into AMS and RF SoCs such as analog-to-digital converters (ADCs) or RF receivers for cognitive radio. By combining its expertise in the physical realization of the CMOS chip with its experience in signal processing and its knowledge of the other network layers for which LTCI’s skills are recognized, the group designs high-performance AMS and RF SoCs. The aim is to develop elements or "building blocks", enabling the system of connected objects to be interfaced on one side with the physical world via sensors, and on the other side with the system core via communications, in particular RF.

References